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50 Commits

Author SHA1 Message Date
Nicolas Clauvelin
8cb2714b4b
Fix typo in API documentation
This commit fixes the register type used in the "Register pack goodies" example.

Closes #16
2024-02-21 20:56:54 -05:00
Nicolas Clauvelin
42bd134067 Update CMake install directives v1.0.0 2022-01-27 14:59:12 -05:00
Nicolas Clauvelin
eb166f16e2 Update documentation for register memory access
This commit adds a mention of the `rw_mem_device` and `ro_mem_device`
that provides access to a register memory.

Closes #15
2022-01-27 13:16:20 -05:00
Nicolas Clauvelin
263bd8913d Project maintenance and review
This commit is a collection of changes related to:

- Code style fixes (including nolint) and formatting.
- Suppression of compiler warnings in bitwise operations.
- Minor edits (e.g. copyright dates).
2022-01-27 12:26:40 -05:00
Nicolas Clauvelin
6433346d01 Merge branch 'cleanup' v0.4 2019-04-24 17:03:09 -04:00
Nicolas Clauvelin
a6f09754ca Add Gitlab templates 2019-04-24 17:02:17 -04:00
Nicolas Clauvelin
c1081a114e Code maintenance
* Revise and simplify most enable_if statements in the project.
* Update code style in all files.
* Update copyright year.
* Add a dedicated Memory.h header with the memory device implementation.
* Update documentation.
* CMake cleanup.
2019-04-24 17:00:57 -04:00
Nicolas Clauvelin
2e0d502674 BUG FIX IN MERGER WRITE IMPLEMENTATION FOR NON CONSTANT VALUES
* For write-only registers the merge write implementation for non-constant values
was properly updating the cache value.
* Unnecessary `inline` have been removed.
v0.3
2018-11-16 09:28:47 -05:00
Nicolas Clauvelin
e59bc356c8 FIX CASE ISSUE v0.2 2018-03-29 06:33:59 -04:00
Nicolas Clauvelin
e763c2bfa8 FIX TYPOS AND OTHER MINOR DETAILS IN PERFORMANCE EXAMPLE
This also adds a link in the README to the performance page.
2018-03-29 06:33:59 -04:00
4b85835035 Removed mention of full example 2018-03-29 06:33:59 -04:00
cd4448b330 Updated to new CPPReg and for the most part done with performance comparison 2018-03-29 06:33:59 -04:00
435e038315 Updated performance.md 2018-03-29 06:33:59 -04:00
5a2a351791 Initial work on comparison 2018-03-29 06:33:59 -04:00
Nicolas Clauvelin
c48108be64
ADD CODE OF CONDUCT 2018-03-21 13:13:24 -04:00
Nicolas Clauvelin
203443c1f8 ADD HARDWARE AND COMPILER REQUIREMENTS TO README
This closes #11.
2018-03-21 13:05:07 -04:00
Nicolas Clauvelin
819a004588 API DOCUMENTATION UPDATED
Register pack loop revised for consistency.
2018-03-20 11:20:42 -04:00
Nicolas Clauvelin
c6c2c5055a UPDATED DOCUMENTATION 2018-03-20 08:38:44 -04:00
Nicolas Clauvelin
8d2cdbf25f UPDATED API DOCUMENTATION
This is related to #12.
2018-03-16 15:09:34 -04:00
Nicolas Clauvelin
5925c223c8 INTERNAL IMPLEMENTATIONS RELOCATED TO AN INTERNALS HEADER
The Internals.h contains the overflow, is_aligned and memory array
implementations.
2018-03-16 14:12:52 -04:00
Nicolas Clauvelin
6085f47115 ADD MISSING NEWLINE 2018-03-16 07:53:14 -04:00
Nicolas Clauvelin
53b74b2b5c FIX QUICK START DOCUMENTATION 2018-03-16 07:53:00 -04:00
Nicolas Clauvelin
8cdc89336f UPDATED SINGLE HEADER 2018-03-15 17:25:06 -04:00
Nicolas Clauvelin
23a5580d2b MINOR FIXES FOR CONSISTENCY PURPOSES 2018-03-15 17:24:03 -04:00
Nicolas Clauvelin
95288090d4 ADD ENUMERATION TYPE FOR SUPPORTED REGISTER SIZES
Register sizes are now represented by an enumeration type. This limits the
possibility to typeset unsupported register sizes, and make the interface easier
to read.

See #12.
2018-03-15 17:13:54 -04:00
Nicolas Clauvelin
c217f34e0c REVISED CHECKS FOR PACKED REGISTER ALIGNMENT
This now relies on a is_aligned implementation. This will needs to be adapted
once register width is defined through an enumeration.

See #12.
2018-03-15 16:16:42 -04:00
Nicolas Clauvelin
1590e7c0e3 UPDATED QUICK START DOCUMENTATION FOR NEW PACK API 2018-03-14 13:15:20 -04:00
Nicolas Clauvelin
6a99ea5de6 UPDATED SINGLE HEADER 2018-03-13 17:44:47 -04:00
Nicolas Clauvelin
7b9a843e2d ADD MORE FUNCTIONALITY TO THE TEMPLATE FOR LOOP IMPLEMENTATION
This adds a C++14 apply method that can be used with polymorphic lambdas.
2018-03-13 17:29:15 -04:00
Nicolas Clauvelin
8ce22c666d REVISED OVERFLOW IMPLEMENTATION USING INTEGRAL CONSTANT
The check_overflow implementation now relies on std::integral_constant.
This avoids the definition of a constexpr bool member.
2018-03-13 17:28:38 -04:00
Nicolas Clauvelin
ee48bbd261 FIX FOR LOOP IMPLEMENTATION AND ADD RANGE LOOP
* Fixes a typo in the for_loop implementation.
* Add a range_loop implementation to help with indexed register pack.
2018-03-13 11:01:34 -04:00
Nicolas Clauvelin
49d19f1b20 FIX TYPO IN PACKED REGISTER STATIC ASSERT 2018-03-13 08:51:23 -04:00
Nicolas Clauvelin
bbdf513156 ADD MIXED REGISTER SIZES SUPPORT TO REGISTER PACK
This relies on a memory map implementation based on std::array and specialized
over the register size. PackedRegister can now be used with all supported
register sizes (i.e., widths).

This relates to #7 and the finalization of the API before performance testing.
2018-03-13 08:48:42 -04:00
Nicolas Clauvelin
ae6da9b7f5 REVISED REGISTER PACK IMPLEMENTATION FOR SIZE ISSUES
The revision brings the support for 16-bits and 32-bits registers.
2018-03-12 22:18:54 -04:00
Nicolas Clauvelin
984d4ceb58 ADD TEMPLATE FOR LOOP IMPLEMENTATION 2018-03-12 17:51:00 -04:00
Nicolas Clauvelin
327e230847 ADD PROPER DOCUMENTATION COMMENTS 2018-03-12 17:20:32 -04:00
Nicolas Clauvelin
4d575c176f UPDATED SINGLE HEADER 2018-03-12 16:37:29 -04:00
Nicolas Clauvelin
154b29bef3 REGISTER PACK FIRST IMPLEMENTATION 2018-03-12 16:35:36 -04:00
Nicolas Clauvelin
e4ae5641ec CPPREG MEMORY ACCESS REVISION
All access to memory are now done through reference (const reference for
read-only access). This is done to facilitate the implementation of register
packs.
2018-03-12 16:35:26 -04:00
Nicolas Clauvelin
f1d98d6bd5 REVISED SHADOW VALUE USING INTEGRAL CONSTANT
This provides a clearer interface compared to defining a constexpr bool member.
2018-03-11 17:34:38 -04:00
Nicolas Clauvelin
058ccbf13d UPDATED DOCUMENTATION FOR REVISED API
This closes #10.
2018-03-11 09:27:03 -04:00
Nicolas Clauvelin
eb9226fe5d API REVISED FOR BETTER READ/WRITE PERFORMANCE
* For trivial read/write operations (over whole register) simpler implementations are now used to avoid unnecessary load/store instructions.
* Merge write implementation has been revised to provide better performance when manipulating constant values.
* `is_set` and `is_clear` are now available for all Field-based types.

This closes #8.
2018-03-09 16:31:56 -05:00
Nicolas Clauvelin
1c27f907a5 FIXES CONSTEXPR STATIC ISSUE WITH GCC 4.8.X
See https://github.com/sendyne/cppreg/issues/2 for a detailed explanation.

This closes #2.
2018-02-23 06:15:58 -05:00
hak8or
816c579d7d Pin in Led::init() should be off before setting pin direction
Super minor, but I figured it might be good to have that looking correct in the getting started guide.
2018-02-23 05:48:37 -05:00
Nicolas Clauvelin
11734b0bf4 FIX POWERPC COMPILATION ISSUE
For some reason compilers other than GCC PowerPC 4.5.8 were not complaining
about the `use_shadow` being (re)defined outside the `Shadow` structure
definition.

This closes #2.
2018-02-22 17:02:59 -05:00
Sendyne Principal Scientist
926eb71df2 Set theme jekyll-theme-cayman 2018-02-22 10:39:37 -05:00
Nicolas Clauvelin
93763cd6ee Merge remote-tracking branch 'github/master' into develop 2018-02-22 10:35:06 -05:00
Nicolas Clauvelin
5cf8a851d8 FIX INLINING OF WRITE CALLS WITH Os ENABLED
The inlining issue was due to a bad template design in the access policies
implementations: the MMIO_t type from the field was used (which is a volatile
type) for all arguments in the write implementation.
The new implementation relies on two template types (one for the register memory
device and another one for the value to be written). This fixes inlining and was
checked on godbolt.
2018-02-22 10:22:51 -05:00
Sendyne dev-team
a31d4a2875 Set theme jekyll-theme-slate 2018-02-20 16:05:48 -05:00
Nicolas Clauvelin
d7404ab946 INITIAL COMMIT v0.1 2018-02-20 15:38:59 -05:00